He Tingbo, a Huawei board member and president of the company's semiconductor business department, unveils the Tau (τ) Scaling Law, on March 25, 2026. Photo: People's Daily/Lin Yuan

A new paper by Huawei's semiconductor segment chief He Tingbo on the company's Tau (τ) Scaling Law presented measurements from the Kirin 2026 chip, showing that transistor density increased by about 55 percent while power consumption fell across several key computing units at comparable performance.

The paper puts heat and power consumption at the center of the discussion over Tau Scaling. Its abstract places heat at the center of the discussion, calling it "the sharpest concern" surrounding Tau Scaling and saying measurements from Kirin chips produced results contrary to that concern. The paper argues that a major source of chip energy consumption lies not only in computation itself, but also in moving data across the chip.

LogicFolding is one of the core technologies Huawei has developed under the Tau Scaling Law. The approach restructures information pathways so that signals travel shorter distances, rather than simply stacking more circuitry. Huawei said in May that the architecture can shorten critical-path wiring and reduce the resistive and capacitive load involved in signal propagation.

The latest paper presents Kirin 2026 as a concrete example. According to data cited by First Financial from the paper, transistor density increased from about 155 million to 238 million transistors per square millimeter, or roughly 55 percent, compared with the previous generation. At comparable performance, NPU power consumption fell by 66 percent, GPU power consumption fell by 58 percent and CPU performance-core power consumption fell by 41 percent.

For the NPU, Kirin 2026 maintained the same 29 TOPS of AI computing performance while operating at a 63-percent lower clock frequency and reducing voltage from 0.85 volts to 0.55 volts. Power consumption fell 66 percent and power density dropped 73 percent. The GPU delivered the same 61 frames per second while running at a voltage about 200 millivolts lower, cutting power use by 58 percent, according to media reports.

The paper does not suggest that folding circuits automatically lowers power density. It cites an earlier folded DSP design in which power consumption for the same workload fell 25 percent, but power density rose 24 percent because the circuit area shrank by 40 percent. By the Kirin 2027 DSP design, power consumption had fallen 47 percent and power density was also below that of the original planar design, the paper said.

Tau is a time scaling law rather than an energy scaling law, meaning that shorter signal paths do not by themselves guarantee lower power use. The timing headroom created by LogicFolding can instead give designers more room to balance performance, area and power — for example, through greater parallelism, lower operating voltage or shorter data paths, according to media reports, citing the paper.

Huawei first presented the Tau Scaling Law at the 2026 IEEE International Symposium on Circuits and Systems in Shanghai on May 25. The company describes the principle as replacing geometric scaling with time scaling, with technologies such as LogicFolding used to reduce signal-propagation delay and steadily increase transistor density.

Huawei said that it had designed and mass-produced 381 chips based on the principle over the previous six years, and that Kirin chips scheduled for launch in the fall of 2026 would be the first to adopt the LogicFolding architecture.

He published an updated V2 version of A Time Scaling Theory for Multi-Layer Electronic Systems on ChinaXiv on July 3. The update further developed the post-Moore's Law scaling framework centered on the time constant τ, while adding engineering implementation pathways, measured data and product roadmaps, according to ChinaXiv. 

Global Times