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Huawei paper details major chip breakthroughs, 100-fold AI scaling target and Kirin 2026 roadmap: report
Published: Jul 05, 2026 08:51 PM
He Tingbo, a Huawei board member and president of the company's semiconductor business department, unveils the Tau (τ) Scaling Law, on March 25, 2026. Photo: People's Daily/Lin Yuan

He Tingbo, a Huawei board member and president of the company's semiconductor business department, unveils the Tau (τ) Scaling Law, on March 25, 2026. Photo: People's Daily/Lin Yuan


He Tingbo, president of Chinese tech giant Huawei's Semiconductor Business Department, updated her paper, "A Time Scaling Theory for Multi-Layer Electronic Systems" on ChinaXiv, the Chinese Academy of Sciences' preprint platform, on Friday, Science and Technology Daily reported.

Compared with the V1 version released on May 25, the updated paper builds on the original theoretical framework by adding extensive engineering implementation details, measured quantitative data, and a product evolution roadmap, further refining a post-Moore scaling theory system centered on the time constant τ, according to the report.

The paper presents two production-scale engineering validation results, according to the report. 

In the field of mobile SoCs (system on chips), it applies "LogicFolding," a design approach that partitions digital, analog and memory circuits into vertically stacked active layers and connects them via ultra-fine bonding, to achieve, at a fixed process node, a step increase of 55 percent in transistor density and a 41 percent improvement in energy efficiency.

Moreover, in the field of AI systems, a co-designed full technology stack including a unified bus architecture with memory semantics (Unified Bus), near package optical I O (Hi ONE), and edge to surface 3D folding is expected to increase hardware integration density by more than 100 times by 2035.

Both sets of data come directly from the main text of the paper and represent the key incremental information in version 2.

The paper also discloses measured power consumption and voltage data for the Kirin 2026 chip based on the "Tau Scaling Law," key process parameters of Logic Folding, as well as specific performance targets for the next four generations of Kirin processors and Ascend AI chips, Science and Technology Daily reported.

In the autumn, Huawei's new devices equipped with the Kirin 2026 chip are expected to be released, entering the market for real world validation, said the report.

Global Times